1. Field of the Invention
The present general inventive concept relates to a memory system, and more particularly, to a memory system having increased storage capacity in a high-speed operating environment.
2. Description of the Related Art
In general, electronic products, such as memory devices, require high-speed data processing. Thus, various methods have recently been introduced to increase operating speeds. In particular, a maximum operating speed of NAND flash memory for use in storage devices, such as solid state drives (SSDs), may be up to 40 Mbps. Also, research is being conducted into development of NAND flash memory that can operate with a maximum data throughput of 133 Mbps.
However, not only an operating speed but also the total number of memory chips to be connected to the same signal line, i.e., the same channel, is a very important factor in NAND flash memory for use in storage devices, such as SSDs. This is because the more memory chips are connected to the same signal line, the greater the storage capacity of NAND flash memory.
However, in a conventional signal line topology, if an operating speed and the total number of memory chips that are to be connected to the same signal line are both increased, then signal integrity may be degraded due to loading effects between a driver and a receiver. That is, input capacitance increases when a frequency is increased in order to increase an operating speed, and load on the system increases when the total number of memory chips that are to be connected to the same signal line is increased, thereby causing a resistance-capacitance (RC) delay to occur.